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TT6297/tt6298 07?/06/20 page 1 of 19 ver :1.0 4-channel adpcm voice syntehsis lsi general description the TT6297/tt6298 is a 4-channel mixing adpcm voice synthesis lsi which offers one sound outputs with 4 channels . the TT6297/tt6298 can access an external voice data rom for sound effects or speech voice. the maximum external rom size is 16m/8m *8 bit and can direct access. the TT6297/tt6298 has an 4-cha nnel synthesis stage which allows the simultaneous playback of four different channels . it is used to have a voice with bgm (back ground music) effect, instrume ntal sound, echo effect etc. features ? a dvance adpcm algorithm ? number of bits/sample: 4 ? 24 address lines (TT6297), 23 address lines (tt6298)for external rom ? 8-bit control bus for mode setting ? external memory capacity 128mbit for TT6297/64mbit for tt6298 ? interface with common cpu and mpu ? clock frequency with sampling fre quency: (clock 1 mhz to 4 mhz) ? at 1.088 mhz clock dao : 8 khz ? at 2.176 mhz clock dao : 16 khz ? at 4.352 mhz clock dao : 32 khz ? number of words: 511 maximum ? vocalization time:TT6297 :64 minutes ma ximum (at 8 khz, sample rate) tt6298 :32 minutes maximum (at 8 khz, sample rate) ? sound output channel (dao with 4 channels) ? built-in da converter: 12-bit ? dao output format: a-class ? voice level attenuation: odb~-24db on each channel (9steps) with -3db/step ? advance low power cmos process ? 5 v or 3.3 v single power supply ? 48-pin plastic ssop
TT6297/tt6298 07?/06/20 page 2 of 19 ver :1.0 block diagram
TT6297/tt6298 07?/06/20 page 3 of 19 ver :1.0 pin configuration tt6298 TT6297 csb dao ssop48 a9 a21 a22 a8 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7 vdd xtb xt i7 i6 i5 i4 i3 i2 i1 i0 a20 a19 a18 a17 a16 a15 a14 a13 a12 a10 a11 48 1 vss rdb wrb resetb csb dao ssop48 a22 a23 a21 a8 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7 vdd a9 xt vss rdb wrb i7 i6 i5 i4 i3 i2 i1 i0 a20 a19 a18 a17 a16 a15 a14 a13 a12 a10 a11 48 1 resetb TT6297 : for external clk input , 24 address lines (a0~a23) external memory capacity 128mbit tt6298 : for crystal osc , 23 address lines (a0~a22) external memory capacity 64mbit
TT6297/tt6298 07?/06/20 page 4 of 19 ver :1.0 pin description pin name pin no TT6297 pin no tt6298 i/o function i 0 ~ i 3 12~15 12~15 i/o i 4 ~ i 7 16~19 16~19 i instruction bus and condition outputs. these pins are inputs for phrase specification maximum number of phrases is 511, l 0 ~ l 3 pins are also outputs of the operati ng state- busy state, for channels 1~4 and are further used to select the channel attenuation rate. wrb 20 20 i write enable input. data is written on the data bus of l 0 ~ l 7 the data is written when wr goes low. rdb 21 21 i read enable input. the output busy state of channels 1~4 on the data bus of l 0 ~ l 3 can be read using this input. a high level indicates busy. csb 22 22 i chip select input. inpu t ?l? level either when wr signal is input or when rd signal is input. resetb 24 24 i reset input. reset condition is available by inputting ?l? level all functions are suspended during reset. a 0~ a 23 / a 22 36~48 1~11 37~48 1~11 o address outputs. these pins are to address the external rom in which voice data is stored. TT6297 : a0~a23 tt6298 : a0~a22 d 0 ~ d 7 28~35 29~36 i voice data inputs. dao 26 27 o voice synthesis output. voice synthesized analog signal is output from this pin. xt 25 25 i external clk input (cry stal oscillator pin.). xtb ? 26 o crystal oscillator pin. vdd 28 28 p power supply pin. vss 23 23 p ground pin.
TT6297/tt6298 07?/06/20 page 5 of 19 ver :1.0 electrical characteristics ? absolute maximum ratings ? recommended operating conditions ? dc characteristics (vdd = 2. 9 ~ 5.5v,vss=0v,ta = -40 ~ 85 c) parameter symbol conditions value unit power supply voltage vdd ta=25 c -0.3~+7.0 v input voltage v in ta=25 c -0.3~vdd +0.3 v storage temperature t stg 7 -55 ~ 150 c parameter symbol conditions value unit power supply voltage vdd vss=0v 2.9 ~ +5.5 v operating temperature t op vss=0v -40 ~ +85 c oscillation frequency f osc vss=0v 1~5 mhz limits parameter symbol conditions min. typ. max. unit ?l? input current i il v il =vss -10 ?h? input current i ih v ih =vdd 10 a ?l? input voltage v il 0.2vdd ?h? input voltage v ih 0.8vdd v ?l? output voltage v ol i lo =0.8ma 0.45 ?h? output voltage v oh i oh =-40 a vdd v output leakage current i lo vss v out vd d -10 10 a operating current i dd f osc =4.0mhz 5 10 ma da output relative error v dae no load 20 mv da output impedance r daout 15 k ?
TT6297/tt6298 07?/06/20 page 6 of 19 ver :1.0 ? ac characteristics vdd = 4.5~5.5v,vss=0v,ta= -40 ~ +85 c) parameter symbol min. typ max. unit clock cycle t cyc 200 - - ns clock duty cycle f duty 40 50 60 % reset pulse width t rel 100 - - ns cs pulse width t csl 250 - - ns wr pulse width t wrl 200 - - ns r d pulse width t rdl 300 - - ns reset fall to cs fall t rc 250 - - ns cs fall to wr fall t cwl 50 - - ns wr raise to cs raise t cwh 0 - - ns data set up time of l 0 - l 7 in respect to wr raise t si 80 - - ns data hold time of l 0 - l 7 in respect to wr raise t hi 80 - - ns r d fall to stable output of l 0 - l 3 t rizo - - 120 ns r d raise to flow status output of l 0 - l 3 t rioz 0 - 120 ns cs fall to r d fall t crl 20 - - ns r d raise to cs raise t crh 0 - - ns address stable (a 0 -a 23 ) to data input of d 0 -d 7 t ad - - 5?t cyc +90 ns
TT6297/tt6298 07?/06/20 page 7 of 19 ver :1.0 timming chart
TT6297/tt6298 07?/06/20 page 8 of 19 ver :1.0 function explanation 1. phrase selection phrase selection phrases are specified and read into the 2 byte data which consists of i 0 ~ i 7 data bus. the phrase selection data is latched when wrb goes high while csb is low .the format of the phrase specification input is as follows. as shown in the above chart, i 7 of the first 1 data byte is always 1. i 0 ~i 6 of the first data byte specifies the low phrase addre ss and the i7,i6 of sec ond byte are used as high phrase address. the phrase selection da ta has a selection of 511 phrases which corresponds to 000000001~111111111. the phrase sele ction data is used for to a 3 ~a 11 address outputs, and they sp ecify both start and stop addre ss which are stored in the external rom. relation between phrase selection data and rom address phrase selection data il 7 il 6 l 6 l 5 l 4 l 3 l 2 l 1 l 0 - - - external rom address a 23 ~a 10 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 selection not valid phrase 1 phrase 2 phrase 3 phrase 510 phrase 511 0~0 0~0 0~0 0~0 0~0 0~0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * phrases can not be specif ied with all inputs = ?0? l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0 1st byte 1 phrase selection data 2nd byte phrase expansion ii6,ii7 & channel specification ii4,ii5 reduction specification ii3~ii0
TT6297/tt6298 07?/06/20 page 9 of 19 ver :1.0 the second byte of data specifies the high phrase address, the synthesis operating channel as well as specific channel reduction of the synthesized play-back. the channel selection format is shown below. it is not possible to specify multiple channels at the same time. phrase expansion bits the data bits ii7 & ii6 of second byt e and the data bits i6 ~i0 of first byte will combine as the total phrase address a11~a3. channel specification $iboofm ii 5 ii 4 reduction specification all zero is considered as 0 db of the relative sound itself. the reduction is made through 9 levels from about 0 db to - 24 db with the steps of about - 3 db. reduction format is shown below. reduction selection attenuation level i 3 i 2 i 1 i 0 e# e# e# e# e# e# e# e# e#
TT6297/tt6298 07?/06/20 page 10 of 19 ver :1.0 2. voice synthesis channel suspension voice synthesis operation of any channel can be suspended. channel suspension is controlled by bits i 3 ~ i 6 of data bytes i 0 ~i 07 . to suspend a channel, make i 7 =0, while i 3 ~ i 6 represent the channels wh ich should be suspended channel suspension occurs even if multiple channels are selected. for example, if i 3 ~ i 6 are all 1 and i 7 =0, then channels 1~4 are suspended simultaneously. suspended channel i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 3 .data rom 1) address data this specifics start and stop address of adpcm speech data. one phrase start and end address consists of 8 bytes. the first 3 bytes show start address while the last 3 bytes show stop addre ss. the other 2 bytes are empty. by selecting the first address in which the start address is stored, the selected speech data is played back. start addresses (sa 1~ sa 3 ) and stop addresses (ea 1 ~ea 3 ) are stored according to the chart shown below address 0 sa 1 address 1 sa 2 address 2 sa 3 address 3 ea 1 address 4 ea 2 address 5 ea 3 address 6 empty address 7 empty d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sa 1 / ea 1 a23 a22 a21 a20 a19 a18 a 17 a 16 sa 2 / ea 2 a 15 a 14 a 13 a 11 a 10 a 15 a 9 a 8 sa 3 / ea 3 a 7 a 6 a 5 a 3 a 2 a 15 a 1 a 0
TT6297/tt6298 07?/06/20 page 11 of 19 ver :1.0 2) adpcm speech data adpcm speech data consists of 4-bit samples. so, 1 byte stores 2 samples. the data arrangement proceeds from higher rank bits (d 4 ~d 7 ) to lower rank bits (d 0 ~d 3 ). the storage of speech data should always be ended with the lower rank bit, so, always store an even number of samples, speech data is produced by speech development tool TT6297/tt6298. 3) data rom structure when 1 phrase is selected, address data is written from rom address 00008h to 0000fh, when the maximum 511 phrases are se lected in address data section, the data is written up to rom address 00fffh. and the rest is used as the adpcm data section. the following chart shows the memory map of the source data rom.
TT6297/tt6298 07?/06/20 page 12 of 19 ver :1.0 functional description 1. phrase selection input this procedure is to input phrase selection data onto the data bus inputs i 0 ~i 7 . the data is latched internally when wr rises from "l" to "h", while csb remains "l". voice synthesis operati on does not start till the second byte is fully latched note j phrase selection is from cha nnel 1 to channel 8 continuously if all of ch1~ch4 cmm are latched, then the dao output arrrox.. 420 tcyc. *1 an interval of 75 t cyc (max.) is needed between phrases note*2 oscillation frequency = 1.088 mhz ss = "l' voice synthesis playback can be started from any channel, l to 8. the arrangement of each channel can be in any order. th e second byte of the phrase selection data contains the phrase attenuation data in bits d 0 - d 3 . synthesized data is a ttenuated in -3 db steps from 0 db to -24 db.
TT6297/tt6298 07?/06/20 page 13 of 19 ver :1.0 2. attenuation of synthesized speech 3. speech synthesis channel suspension this is accomplished by writing the synthesis channel suspension data onto data bus inputs i 3 ~i 7 the data is latched internally when wr goes from "l" to "h" while csb remains active (l). since synthesis suspensi on data is 1 byte data, synthesis operation is suspended right after the rising edge of wr . multiple channels can be specified, making it possible to suspend channels 1~4 simultaneously. note: * oscillation frequency = 1.088 mhz ss= ?l?
TT6297/tt6298 07?/06/20 page 14 of 19 ver :1.0 4. reading the busy status while csb is "l" and rd is "l", each operation state, the busy state of channels 1~4 is output on i 0 ~i 3 . "h" is output during synthesized playback. 5. start and stop of 1 channel start and stop of signal channel when a single channel (either of channels 1-4) starts again after it has stopped, the first write for start must be input with a delay of more than one sample rate from the stop write as shown in the figure above. when stop is entered, voice playback stops all the next sample and bu sy becomes "l" when start is entered again, voice is output after 238 + ( the reverse of ss pi n ) x 34 clock from the second byte write. busy becomes "h" afte r 35 clock internally
TT6297/tt6298 07?/06/20 page 15 of 19 ver :1.0 start and stop in plural channels when channels are operating, the first byte write for start must be input with a delay of more than one sample rate from stop writi ng. the channel where stop was input, stops at every sample. voice off the channel where stop was again input is output after a maximum 2 samples l clocks from the preceding sample point. the busy signal becomes "h " state after the 35 clock + maximum 2 samples time.
TT6297/tt6298 07?/06/20 page 16 of 19 ver :1.0 application circuit for TT6297 TT6297 : for external clk input , 24 address lines (a0~a23) external memory capacity 128mbit reference only
TT6297/tt6298 07?/06/20 page 17 of 19 ver :1.0 application circuit for tt6298 tt6298 : for crystal osc , 23 address lines (a0~a22) external memory capacity 64mbit reference only
TT6297/tt6298 07?/06/20 page 18 of 19 ver :1.0 (48 pin ssop)
TT6297/tt6298 07?/06/20 page 19 of 19 ver :1.0 revise history 1. 2007/6/20 (v1.0) -original version

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